Ian's Blog - Electronics-FPGA-CPLDOh god... how did this get here? I am not good with computer.tag:joshianlindsay.com,2005:63187d1266ad21283196e7e2f3ed692f/Electronics-FPGA-CPLDTextpattern2023-12-09T10:30:40ZIanhttp://joshianlindsay.com/Ian2016-07-04T07:03:57Z2016-08-19T07:56:09ZCPLD is ready-to-rocktag:joshianlindsay.com,2016-08-19:63187d1266ad21283196e7e2f3ed692f/3196718cf68952638c7250bc5438dae1
As of today, the CPLD is a solved-problem. All the design goals detailed in my prior post are satisfied and have been tested up-to ~5MHz input clock. ]]>
Ian2009-05-16T08:39:39Z2018-11-28T03:02:59ZIDE Interface in a Xilinx 9572 CPLDtag:joshianlindsay.com,2009-05-16:63187d1266ad21283196e7e2f3ed692f/fed5a03ce2f9580356af7c3fe64ff927
This is my first attempt at making an actual ASIC.]]>